Bio-inspired way to grow graphene for electronic devices


BioGraphene-320Dr. Gao (left) and research assistant Ms Lim Xiao Fen working on the wafer-scale graphene growth and transfer in the Graphene Research Centre’s clean roomGraphene, a form of two-dimensional carbon, has many desirable properties that make it a promising material in many applications. However, its production especially for high-end electronics such as touch screens faces many challenges. This may soon change with a fresh approach developed by National Univ. of Singapore (NUS) researchers that mimics nature.

Inspired by how beetles and tree frogs keep their feet attached to submerged leaves, the findings published recently in Nature revealed a new method that allows both the growth and transfer steps of graphene on a silicon wafer. This technique enables the graphene to be applied in photonics and electronics, for devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers.

Professor Loh Kian Ping, Head of the NUS Department of Chemistry, led a team to come up with the one-step method to grow and transfer high-quality graphene on silicon and other stiff substrates. This promises the use of graphene in high-value areas where no technique currently exists to grow and transfer graphene with minimal defects for use in semiconductors.

Prof Loh, who is also a Principal Investigator with the Graphene Research Centre at NUS Faculty of Science, explained: “Although there are many potential applications for flexible graphene, it must be remembered that to date, most semiconductors operate on “stiff” substrates such as silicon and quartz.”

Thus, a transfer method with the direct growth of graphene film on silicon wafer is needed for enabling multiple optoelectronic applications, he said.

In the process called “face-to-face transfer”, Dr. Gao Libo, the first author who is with the Graphene Research Centre, grew graphene on a copper catalyst layer coating a silicon substrate. After growth, the copper is etched away while the graphene is held in place by bubbles that form capillary bridges, similar to those seen around the feet of beetles and tree frogs attached to submerged leaves. The capillary bridges help to attach the graphene to the silicon surface and prevent its delamination during the etching of the copper catalyst.

The novel technique can potentially be deployed in batch-processed semiconductor production lines, such as the fabrication of large-scale integrated circuits on silicon wafers.

The researchers will be fine-tuning the process to optimise the high throughput production of large diameter graphene on silicon, as well as target specific graphene-enabled applications on silicon. They are also looking at applying the techniques to other two-dimensional films.

Source: National Univ. of Singapore

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Riding an electron wave: The Future of Microchip Fabrication?


Printing Graphene Chips(Nanowerk News) Advanced plasma-based etching is a key  enabler of Moore’s Law that observes that the number of transistors on  integrated circuits doubles nearly every two years. It is the plasma’s ability  to reproduce fine patterns on silicon that makes this scaling possible and has  made plasma sources ubiquitous in microchip manufacturing.
A groundbreaking fabrication technique, based on what is called  a DC-augmented capacitively coupled plasma source, affords chip makers  unprecedented control of the plasma. This process enables DC-electrode borne  electron beams to reach and harden the surface of the mask that is used for  printing the microchip circuits. More importantly, the presence of the beam  creates a population of suprathermal electrons in the plasma, producing the  plasma chemistry that is necessary to protect the mask. The energy of these  electrons is greater than simple thermal heating could produce—hence the name  “suprathermal.” But how the beam electrons transform themselves into this  suprathermal population has been a puzzle.
Plasma Wave Spectrum
A  plasma wave can give rise to a population of suprathermal electrons. (Credit:  I.D. Kaganovich and D. Sydorenko)
Now a computer simulation developed at the U.S.  Department of Energy‘s Princeton
Plasma Physics Laboratory in collaboration with the University  of Alberta has shed light on this transformation. The simulation reveals that  the initial DC-electrode borne beam generates intense plasma waves that move  through the plasma like ripples in water. And it is this beam-plasma instability  that leads to the generation of the crucial suprathermal electrons.
Understanding the role these instabilities play provides a first  step toward still-greater control of the plasma-surface interactions, and toward  further increasing the number of transistors on integrated circuits. Insights  from both numerical simulations and experiments related to beam-plasma  instabilities thus portend the development of new plasma sources and the  increasingly advanced chips that they fabricate.
Abstracts
55th Annual Meeting of the APS Division of Plasma  Physics
TO6.00005 Collisionless acceleration of plasma electrons by  intense electron beam
Session: Low Temperature Plasma Science, Engineering and  Technology
9:30 AM–11:06 AM, Thursday, November 14, 2013
Source: American Physical Society 

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RMIT University, Australia:The Formation of Nanofins from Magnetic Nanoparticles: Video


Printing Graphene ChipsPublished on Oct  2, 2013

Heat has become one of the most critical issues in computer and semiconductor design: The ever increasing number of transistors in computer chips requires more efficient cooling approaches for the hot spots which are generated as a result of the operation of the transistors. Researchers at RMIT University in Australia have demonstrated a microfluidic technique of using thermally conductive and magnetic chromium oxide nanoparticles that can form low-dimensional fins in the vicinity of hot spots.

Read more at http://www.nanowerk.com/spotlight/spo…

Watch the Video Here:

Computer Chips Get Smaller .. Cost Less .. with Nanotechnology


Printing Graphene Chips(Nanowerk News) Not so long ago, a computer filled a  whole room and radio receivers were as big as washing machines. In recent  decades, electronic devices have shrunk considerably in size and this trend is  expected to continue, leading to enormous cost and energy savings, as well as  increasing speed.
Key to shrinking devices is Terascale computing, involving  ultrafast technology supported by single microchips that can perform trillions  of operations per second.
Using Terascale technology, semiconductor components commonly  used to make integrated circuits for all kinds of appliances could measure less  than 10 nanometres within several years. Keeping in mind that a nanometre is  less than 1 billionth of a metre, electronic devices have the potential to  become phenomenally smaller and require significantly less energy than today – a  development that will revolutionise the electronics industry.
Despite progress, the technology for producing these ultra-small  devices has a long way to go before being reliable. To advance the work, the  EU-funded project TRAMS (‘Terascale reliable adaptive memory  systems’) sought to improve reliability by improving chip design.
The TRAMS team conducted in-depth variability and reliability  analyses to develop chip circuits that are much less prone to errors. These  circuits feature new designs that yield reliable memory systems from currently  unreliable nanodevices.
The main challenge was to develop reliable, energy efficient and  cost effective computing using a variety of new technologies with individual  transistors potentially measuring below five nanometres in size.
The team investigated a number of technologies and materials  with potential to make Terascale computing a reality. These included:
  • carbon  nanotubes;
  • new  transistor geometries, such as FinFETs;
  • state-of-the-art  nanowires, which offer very advanced transistor capabilities for use in a new  generation of electronic devices.
Using models, the researchers analysed reliability – from the  technology to the circuit level.
These advances are expected to redefine today’s standard  ‘complementary metal-oxide semiconductors’ (CMOS). The team’s results would help  Europe’s manufacturers develop CMOS devices below the 16 nanometre range. The  biggest challenge will lie in reducing CMOS devices to below five nanometres – a  development that now starts to look possible.
From communication and security to transport and industry,  CMOS-based devices of the future promise to redesign the technology we use,  introducing radical energy and cost savings.
The TRAMS consortium includes universities and companies from  Spain, Belgium and the UK. The project was coordinated by Spain’s Universitat  Politècnica de Catalunya, and received almost EUR 2.5 million in EU funding. The  team concluded its work in December 2012.
Source: Cordis

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Nanotubes Seen as Alternative When Silicon Chips Hit Their Limits


By 
Published: February 19, 2013   Bits

Mega UploadsSAN FRANCISCO — In the next decade or so, the circuits etched on silicon-based computer chips are expected to shrink as small as they can physically become, prompting a search for alternative materials to take their place.

Some researchers are putting high hopes on carbon nanotubes, and on Monday a group of researchers at Stanford successfully demonstrated a simple microelectronic circuit composed of 44 transistors fabricated entirely from the threadlike fibers.

The development, which was presented both as a paper and a working demonstration at a technical conference here, is the most striking evidence yet that carbon nanotubes may prove to be the material of the future when today’s silicon-based chips reach their fundamental physical limits.

I.B.M., which is one of the biggest proponents of nanotubes for microelectronic applications, has made clear its hope that carbon nanotube technology will be ready a decade from now, when semiconductors are expected to shrink to minimum dimensions of just 5 nanometers. But until now, researchers at universities and chip makers have succeeded in making only individual devices, like transistors, from carbon nanotubes.

The Stanford development is the first time a complete working circuit has been created and publicly demonstrated, suggesting that the material may indeed live up to its promise.

Silicon, a plentiful natural element that functions both as a conductor and an insulator, has already lasted decades longer than computer engineers originally expected, as generations of increasingly smaller transistors have been perfected. It is used by the computer chip industry to etch circuits much finer than the wave length of light, and engineers and scientists say they believe that the material will continue to scale down, at least until the end of the decade.

But sooner or later the shrinking of circuits made from the material will stop, ending the microelectronic era that has been defined by Moore’s Law, the 1965 observation by the Intel co-founder Gordon Moore that the number of transistors that could be placed on a silicon chip doubled at regular intervals.

The Stanford advance seems to hold promise for the belief that whenever the silicon era stalls, the scaling-down process will continue, and permit designers to increase power and capacity of computers far into the future.

The Stanford demonstration came during a session at the International Solid State Circuits Conference, held here annually. A graduate student, Max Shulaker, chose a wooden, human-size hand, connected to a simple motor and gear arrangement on a makeshift stand. Onstage, he threw a switch and the hand shook vigorously.

It was a simple demonstration, but the research group said its goal was to build an entire microprocessor from carbon nanotubes to confirm the potential of the material.

Besides their small size, carbon nanotubes use much less power and switch faster than today’s silicon transistors.

“The bottom line is you can expect an order of magnitude in power saving at the system level,” said Subhasish Mitra, an associate professor of electrical engineering at Stanford and director of the Robust Systems Group. That offers tremendous promise for effectively increasing the battery life in mobile consumer devices in the future, he said.

Other new materials and variations of silicon-based transistors are also being studied to see if they will shrink to smaller sizes. Intel, for example, last year began using a three-dimensional transistor called a FinFET. By turning the device on its side, the chip maker was able to pack transistors more densely on the surface of a chip.

“I’m not saying there is nothing else around,” said H.-S. Philip Wong, a Stanford electrical engineering professor. “It’s just a matter of who wins when you scale down to really, really small dimensions.”

The challenge of carbon nanotubes in their type state is that they form a giant “hairball” of interwoven molecules. However, by chemically growing them on a quartz surface, the researchers are able to align them closely and in regularly spaced rows. They then transfer them to a silicon wafer, where they used conventional photolithographic techniques to make working circuits.

The technological hurdle has been to make reliable circuits even when a small percentage of the wires are misaligned. The Stanford group stated it had perfected a circuit technique that made use of redundancy to work around the imperfectly formed wires.

Dr. Mitra said that “99.5 percent looks very nice on a PowerPoint slide. But when you’re talking about 10 billion things, .5 percent of 10 billion is a really large number, and that completely messes things up.”

Beyond microelectronics, carbon nanotubes are showing promise in commercial applications like rechargeable batteries, bicycle frames, ship hulls, solar cells and water filters, according to an article in the Feb. 1 issue of the journal Science.

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A version of this article appeared in print on February 20, 2013, on page B4 of the New York edition with the headline: Nanotubes Seen as Alternative When Silicon Chips Hit Their Limits.

Will it be possible someday to build a ‘Fab-on-a-Chip’?


 

QDOTS imagesCAKXSY1K 8(Nanowerk Spotlight) Semiconductor fabs are large,  complex industrial sites with costs for a single facility approaching $10B. In  this article we discuss the possibility of putting the entire functionality of  such a fab onto a single silicon chip.

 

We demonstrate a path forward where, for  certain applications, especially at the nanometer scale, one might consider  using a single chip approach for building devices, both integrated circuits and  nano-electromechanical systems.  Such methods could mean shorter device  development and fabrication times with a significant potential for cost savings.  In our approach, we build micro versions of the macro machines one typically  finds in a fab, allowing for the functionality to be placed on a single silicon  substrate.  We argue that the technology will soon exist to allow one to build a  “Fab on a Chip”.

Moore’s Law is a well-known concept.  According to the  observation first made by Gordon E. Moore, Intel’s then CEO, the number of  transistors on an IC doubles roughly every two years1.  Less well known is Rock’s Law, sometimes called  Moore’s Second Law, which says that semiconductor fabrication facilities, or  fabs, double in cost roughly every four years2.

Current typical costs for a state-of-the-art fab range from $3-4B and can even  reach up to ~$9.3B for TSMC’s recent 300mm fab in Taiwan3.  Eventually Rock’s Law must run into Herbert Steins’ observation that  “If  something cannot go on forever, it will stop”.  What can or will happen to  semiconductor fabs before their costs exceed the GDP of the planet?    A standard answer among nanotechnology researchers is that  chemically or biologically inspired “bottom-up” approaches will be developed  that will allow us to grow very-large-scale integration (VLSI) circuits in the  same way we currently grow carbon nanotubes4,  tomatoes or chickens.

Here, the question we pose is whether another approach to  solving this problem is feasible.  Would it be possible to place the entire  functionality of a semiconductor fab on a single silicon chip?  In the same way  as we can contemplate building a “Lab on a Chip”, can we build a “Fab on a Chip”  (FoC)?

For the impatient among you, we will argue here that the answer is  likely to be a qualified “yes”.   As semiconductor technologies continue to shrink from the deep  sub-micron regime into the nanometer regime, standard techniques to manufacture  the devices are becoming more and more challenging. The conventional methods  using photo resist, liftoff and optical/deep-UV/E-beam lithography5,  6 have created the need for multi-billion dollar fabs, but they have no  hope of ultimately scaling into the regime of single or few atom devices.

However, it is clear that progress in device physics is advancing such that in  the not too distant future, we will need and desire single atom devices7 despite the fact that we have no clear idea of how  such circuits could be made using a manufacturable process.

           Scanning electron micrographs of MEMS device

Scanning electron micrographs of MEMS devices that may be  included in a FoC. Clockwise from the top: Linear Actuators and springs provide  nanoscale position control, thermometers and heaters control the surface temperature. A MEMS  controlled near-field scanning optical microscope can image in situ deposited  structures.  Thermal sources provide an atom flux that is detected by mass sensors for  controlled deposition rates. Masks and dynamic shutters guide the atom flux with  both high special and temporal accuracy‡. (Figures are compiled from the work of  J. Chang, B. Corman, K. Frink, H. Han, M. Imboden, and references [11,21]).  (click image to enlarge)  

Our suggested approach is to build MEMS micro versions of the  various systems one finds in a semiconductor fab.  These various elements can  then be placed on a silicon die allowing one to build devices with nano-scale  features.  What does a fab actually do?  At the meta level it takes silicon  wafers and grows arrays of transistors upon them with the appropriate electrical  interconnects.  Could a “Fab on a Chip” do this?  Yes, it could.  Is a “Fab on a  Chip” ever going to build a 10 cm2 square  silicon VLSI die with 1010 CMOS transistors on  it?

Probably not, but one could imagine using a “Fab on a Chip” to build a  square mm device with 108 nano-scale single  electron transistors on it with the appropriate interconnects.  If this later  type of device is of interest to you, a “Fab on a Chip” might be just the thing.

Where between these two limits the FoC technology will run out of gas is  currently an open but interesting question.   A key feature to FoC technology is that one will not use  photoresist and liftoff techniques.  This is an enormous simplification in terms  of reducing the complexity of the traditional fab.  For a FoC, the deposition  step uses a direct write approach8-12.

There  are a number of possible methods.  One such a device is shown in the figure.  It  is a MEMS plate with an integrated shutter allowing for the direct writing of  atoms, analogous to a micro 3-D printer11, 13.   This (or something like it) would be the lithography tool with nanoscale  displacement resolution.  In addition to the lithography tool, one needs sources  of atoms (thermally sourced from micro-heaters14 or ions from micro-spray emitters15),  film thickness monitors based on mechanical oscillators for controlled  deposition16-18, resistive heaters9,19,  thermometers20, shutters/masks, imaging  tools21 and electrical interconnects  that all  work together to monitor and control the fabrication environment and possibly  even including an integrated power source22.

Examples of such MEMS elements are also shown in the figure.  All the devices  can be placed onto a single silicon die and together, could be used to create a  nano-scale system of devices.  The devices shown in the figure were built using  a commercial foundry and can be easily arrayed on a single silicon die23, resulting in a so-called “system of systems”  approach.

Many questions abound such as: Would such chips be cost effective?   High yield? Reliable?  Low Waste? Are we insane to suggest this?  At the moment  the answer these and many other similar questions is “maybe”.

In a very real sense, what we are suggesting is using  macro-machines to build micro-machines and then using these micro-machines to  build nanostructure elements of electrical circuits and nano-electromechanical  systems.  The concept of producing micron-scale MEMS devices (which cost roughly a dollar per square mm to  produce, and perhaps even a factor of ten less in large volumes) and then using  nanometer tunability to create nano-scale devices opens up a new and perhaps  much less expensive avenue towards manufacturing large arrays of nano-scale  devices. 

We  believe it is fair to call this approach a “Fab on a Chip” because in addition  to the lithography piece, one can integrate onto the silicon chip many of the other functions a semiconductor fab  performs and at the end of the day, these chips would produce what fabs produce:  a silicon die with arrays of devices on them.

Will such an approach be a “holy grail” that solves all the  problems associated with producing nano-scale VLSI circuits?  Probably not.   Will it allow us to produce certain types of nano-scale circuits in a cost  effective way?  We believe so.  Is it an interesting and potentially important  avenue to research?  Absolutely.  

Notes 1. Moore, G. The Future of Integrated Electronics. Fairchild  Semiconductor internal publication (1964).   2. Rupp, K. & Selberherr, S. The  economic limit to Moore’s law. Semiconductor Manufacturing, IEEE  Transactions on 24, 1-4 (2011).   3. TSMC Begins Construction on Gigafab™ In Central  Taiwan 4. Li, X., Cao, A., Jung, Y. J., Vajtai, R. & Ajayan, P. M.  Bottom-up growth of carbon nanotube multilayers:  unprecedented growth. Nano Letters 5, 1997-2000 (2005).   5. Ito, T. & Okazaki, S. Pushing the limits of lithography. Nature 406,  1027-1031 (2000).   6. Grigorescu, A. & Hagen, C. Resists  for sub-20-nm electron beam lithography with a focus on HSQ: state of the  art. Nanotechnology 20, 292001 (2009).   7. Rossier, J. F. Single-atom devices: Quantum engineeringNature Materials 12, 480-481 (2013).   8. Lee, W., et al. Direct-write polymer nanolithography in ultra-high  vacuum. Beilstein Journal of Nanotechnology 3, 52-56 (2012).   9. Savu, V., Xie, S. & Brugger, J. 100  mm dynamic stencils pattern sub-micrometre structures. Nanoscale 3,  2739-2742 (2011).   10. Meister, A., Liley, M., Brugger, J., Pugin, R. &  Heinzelmann, H. Nanodispenser for attoliter volume deposition using  atomic force microscopy probes modified by focused-ion-beam millingAppl.Phys.Lett. 85, 6260-6262 (2004).   11. Imboden, M., et al. Atomic Calligraphy: The Direct Writing of Nanoscale  Structures using MEMS. Nano Letters (2013). Also see Nanowerk  Spotlight: “Atomic  calligraphy – using MEMS to write nanoscale structures”.   12. Tseng, A. A. Advancements and challenges in development of atomic  force microscopy for nanofabrication. Nano Today 6, 493-509 (2011).   13. Egger, S., et al. Dynamic shadow mask technique: A universal tool for  nanoscience. Nano Letters 5, 15-20 (2005).   14. Darhuber, A. A., Valentino, J. P., Troian, S. M. &  Wagner, S. Thermocapillary actuation of droplets on chemically  patterned surfaces by programmable microheater arrays. Journal of  Microelectromechanical Systems, 12, 873-879 (2003).   15. Krpoun, R., Smith, K. L., Stark, J. P. & Shea, H. Tailoring the hydraulic impedance of out-of-plane  micromachined electrospray sources with integrated electrodesAppl.Phys.Lett. 94, 163502-163502-3 (2009).   16. Chaste, J., et al. A nanomechanical mass sensor with yoctogram  resolution. Nature Nanotechnology (2012).   17. Lang, H. P., Hegner, M. & Gerber, C. Cantilever  array sensors. Materials today 8, 30-36 (2005).   18. Arcamone, J., et al. Full-wafer fabrication by nanostencil lithography of  micro/nanomechanical mass sensors monolithically integrated with CMOSNanotechnology 19, 305302 (2008).   19. Laconte, J., Dupont, C., Flandre, D. & Raskin, J. SOI CMOS compatible low-power microheater  optimization for the fabrication of smart gas sensors. Sensors  Journal, IEEE 4, 670-680 (2004).   20. Jha, C., et al. CMOS-compatible dual-resonator MEMS temperature  sensor with milli-degree accuracy. Solid-State Sensors, Actuators and  Microsystems Conference, 2007. TRANSDUCERS 2007. 229-232 (2007).   21. Aksyuk, V. A., Barber, B. P., Gammel, P. L. & Bishop, D.  J. Construction of a fully functional NSOM using MUMPs  technology. Proceedings Volume 3226: Microelectronic Structures and MEMS for  Optical Processing III, 188-194 (1997).   22. Pikul, J. H., Zhang, H. G., Cho, J., Braun, P. V. &  King, W. P. High-power lithium ion microbatteries from  interdigitated three-dimensional bicontinuous nanoporous electrodes.

Nature Communications 4, 1732 (2013).   23.

http://www.memscap.com/products/mumps/polymumps/reference-material                       By Matthias Imboden and David Bishop, Department of Electrical and Computer  Engineering, Division of Materials Science and Engineering, Department of  Physics, Boston University

Read more: http://www.nanowerk.com/spotlight/spotid=31758.php#ixzz2buaHWFKT

 

Flexible electronics could transform the way we make and use electronic devices


Flexible electronics open the door to foldaway smartphone displays, solar cells on a roll of plastic and advanced medical devices — if we can figure out how to make them.

QDOTS imagesCAKXSY1K 8Nearly everyone knows what the inside of a computer or a mobile phone looks like: A stiff circuit board, usually green, crammed with chips, resistors, capacitors and sockets, interconnected by a suburban sprawl of printed wiring.

But what if our printed circuit board was not stiff, but flexible enough to bend or even fold?

It may sound like an interesting laboratory curiosity, but not to Enrique Gomez, an assistant professor of chemical engineering at Penn State. “It could transform the way we make and use electronic devices,” he says.

Gomez is one of many scientists investigating flexible electronics at the University’s Materials Research Institute. Others are doing the same at universities and corporations around the world.

Flexible electronics are in vogue for two reasons.

First, they promise an entirely new design tool. Imagine, for example, tiny smartphones that wrap around our wrists, and flexible displays that fold out as large as a television. Or photovoltaic cells and reconfigurable antennas that conform to the roofs and trunks of our cars. Or flexible implants that can monitor and treat cancer or help paraplegics walk again.

Penn State’s interest in flexible and printed electronics is not just theoretical. In October 2011, the University began a multi-year research project with Dow Chemical Corporation. Learn more about the partnership.

Second, flexible electronics might cost less to make. Conventional semiconductors require complex processes and multi-billion dollar foundries. Researchers hope to print flexible electronics on plastic film the same way we print ink on newspapers.

“If we could make flexible electronics cheap enough, you could have throwaway electronics. You could wear your phone on your clothing, or run a bioassay to assess your health simply by wiping your nose with a tissue,” Gomez says.

Before any of this happens, though, researchers have to rethink what they know about electronics.

Victim of Success

That means understanding why conventional electronics are victims of their own success, says Tom Jackson, Kirby Chair Professor of Electrical Engineering. Jackson should know, because he helped make them successful. Before joining Penn State in 1992, he worked on IBM‘s industry-leading laptop displays. At Penn State, he pioneered the use of organic molecules to make transistors and electronic devices.

Modern silicon processors integrate billions of transistors, the semiconductor version of an electrical switch on tiny slivers of crystalline silicon.

Squeezing so many transistors in a common location enables them to handle complex problems. As they shrink in size, not only can we fit more transistors on a chip, but the chip gets less expensive to manufacture.

“It is hard to overstate how important this has been,” Jackson explains.

“Remember when we paid for long-distance phone calls by the minute? High-speed switching drove those costs way down. In some cases, we can think of computation as free. You can buy an inexpensive calculator at a store for $1, and the chip doesn’t even dominate the cost. The power you get is amazing.”

That, says Jackson, is the problem. Semiconductor processors are so good and so cheap, we fall into the trap of thinking they can solve every problem.

Sometimes, it takes more flexibility to succeed.

Electronics-research-001

Consider surgery to remove a tumor from a patient’s liver. Even after following up with radiation or chemotherapy, the surgeon is never sure if the treatment was successful.

“But suppose I could apply a flexible circuit to the liver and image the tissue. If we see a new malignancy, it could release a drug directly onto that spot, or heat up a section of the circuit to kill the malignant cells. And when we were done, the body would resorb the material,” Jackson says.

“What I want,” he says, “is something that matches the flexibility and thermal conductivity of the body.” Conventional silicon technology is too stiff and thermally conductive to work.

Similarly, large, flexible sensors could monitor vibrations on a bridge or windmill blade and warn when they needed maintenance.

“If you want to spread 100 or 1,000 sensors over a large area, you have to ask whether you want to place all the chips you need to do that, or use low-cost flexible electronics that I can apply as a single printed sheet,” Jackson says.

None of the flexible electronics now under development would match the billions of transistors that now fit on silicon chips, or their billions of on-off cycles per second. They would not have to. After all, even today’s fastest televisions refresh their displays only 240 times per second. That is more than fast enough to image cancer in the body, reconfigure an antenna, or assess the stability of a bridge.

So how, exactly, do we make flexible electronics, and what kind of materials do we make them from?

Printing

To explain what draws researchers to printing flexible electronics, Jackson walks through the production of flat panel displays in a $2-3 billion factory.

The process starts with a 100-square-foot plate of glass. To apply wires, the factory coats the entire plate with metal, then covers it with a photosensitive material called a resist. An extremely bright light flashes the pattern of the wires onto the coating, hardening the resist. In a series of steps, the factory removes the unhardened resist and metal under it. Then, in another series of steps, it removes the hardened resist, leaving behind the patterned metal wires.

Factories repeat some variant of this process four or five times as they add light-emitting diodes (LEDs), transistors and other components. With each step, they coat the entire plate and wash away unused materials. While the cost of a display is 70 percent that of a finished device, most of those materials get thrown away.

None of the flexible electronics now under development would match the billions of transistors that now fit on silicon chips, or their billions of on-off cycles per second. They would not have to.

“So it’s worth thinking about whether we can do this by putting materials where we need them, and reduce the cost of chemicals and disposal. It is a really simple idea and really hard to do,” Jackson says.

An ideal way to do that, most researchers agree, would be to print the electronics on long plastic sheets as they move through a factory. A printer would do this by applying different inks onto the film. As the inks dried, they would turn into wires, transistors, capacitors, LEDs and all the other things needed to make displays and circuits.

That, at least, is the theory. The problem, as anyone who ever looked at a blurry newspaper photograph knows, is that printing is not always precise. Poor alignment would scuttle any electronic device. Some workarounds include vaporizing or energetically blasting materials onto a flexible sheet, though this complicates processing.

And then, of course, there are the materials. Can we print them? How do we form the precise structures we need? And how do we do dry and process them at temperatures low enough to keep from melting the plastic film?

Material World

Fortunately, there are many possible materials from which to choose. These range from organic materials, like polymers and small carbon-based molecules, to metals and even ceramics.

At first glance, flexible ceramics seem like a stretch. Metals bend, and researchers can often apply them as zigzags so they deform more easily.

Try flexing a thick ceramic, though, and it cracks. Yet that has not deterred Susan Trolier-McKinstry, a professor of ceramic science and engineering and director of Penn State’s W.M. Keck Smart Materials Integration Laboratory.

Ceramics, she explains, are critical ingredients in capacitors, which can be used to regulate voltage in electronic circuits. In many applications, transistors use capacitors to provide instantaneous power rather than waiting for power from a distant source.

Industry makes capacitors from ultrafine powders. The tiniest layer thicknesses are 500 nanometers, 40 times smaller than a decade or two ago. Even so, there is scant room for them on today’s overcrowded circuit boards, especially in smartphones. Furthermore, there is a question about how long industry can continue to scale the thickness in multilayer ceramic capacitors.

Trolier-McKinstry thinks she can deposit smaller capacitors directly onto flexible sheets of plastic, and sandwich these in flexible circuit board. That way, the capacitors do not hog valuable surface area.

One approach is to deposit a precursor to the capacitor from a solution onto a plastic film and spot heat each capacitor with a laser to remove the organics and crystallize the ceramic into a capacitor. Another approach is to use a high-energy laser beam to sand blast molecules off a solid ceramic and onto a plastic substrate.

As long as she can keep capacitor thicknesses small, Trolier-McKinstry need not worry too much about capacitor flexibility. Previous researchers have demonstrated that it is possible to bend some electroceramic films around the radius of a Sharpie pen without damage.

Of course, not every element placed on a flexible substrate will be small. So what happens if your transistors need to bend?

One way to solve that problem is to make electronics from organic materials like plastics. These are the ultimate flexible materials. While most organics are insulators, a few are conductive.

“Organic molecules have tremendous chemical versatility,” Gomez explains. “My group’s goal is to turn these molecules into transistors and photovoltaic cells.” Easier said than done. The almost infinite number of possibilities available in organic chemistry, he says, make it challenging to find the right combination of structure, properties and function to create an effective device.

Molecules may not be picky about their neighbors, but they still need to form the right type of structures to act as switches or turn light into electricity. Gomez attacks the problem by using a technique called self-assembly. It starts with block copolymers, combinations of two molecules with different properties bound together in the middle.

Trolier-McKinstry thinks she can deposit smaller capacitors directly onto flexible sheets of plastic, and sandwich these in flexible circuit boards. That way, the capacitors do not hog valuable surface area.

“Think of them as a dog and a cat tied together by their tails,” Gomez explains. “Ordinarily, they want to run away from each other, but now they can’t. Then we throw them into a room with other tied dogs and cats. What happens is that all the cats wind up on one side of the room and the dogs on the other, so they don’t have to look at each other.”

Gomez believes this process could enable him to build molecules programmed to self-assemble into electronic structures at very low cost.

“The overarching problem,” Gomez continues, “is figuring out how to design the molecule and then tickle it with pressure, temperature and electrical fields to form useful structures. We don’t really understand enough to do that yet.”

Despite the challenge, flexible electronics promise changes that go beyond folding displays, inexpensive solar cells, antennas and sensors. They could veer off in some unexpected directions, such as helping paraplegics walk again.

Mimicking Jell-O

That is the goal of Bruce Gluckman, associate director of Penn State’s Center for Neural Engineering. To get there, he must learn how the brain’s neurons collaborate.

“Computations happen at the level of single neurons that connect to other neurons. Half the brain is made up of the wiring for these connections, and any cell can connect to a cell next to it or to a cell across the brain. It’s not local in any sense,” he explains.

Scientists measure the electrical activity of neurons by implanting silicon electrodes into the brain. Unfortunately, Gluckman says, the brain is as spongy as Jell-O and the electrode is as stiff as a knife.

Plunging the electrode into the brain causes damage immediately. Every time the subject moves its head, the brain pulls away from the electrode on one side and makes better contact on the other. It takes racks of electronics to separate the signal from the noise of such inconsistent output.

“This is why we need something other than silicon,” Gluckman says.

Despite the challenge, flexible electronics promise changes that go beyond folding displays, inexpensive solar cells, antennas and sensors. They could veer off in some unexpected directions, such as helping paraplegics walk again.

Flexible electronics would better match the brain’s springiness. While some researchers are looking at all-organic electrodes, Gluckman believes they are too large and too slow to achieve the resolution he needs. Instead, he has teamed with Jackson to develop a flexible electrode based on zinc oxide, a faster semiconductor that can be deposited on plastic at low temperatures.

The work is still in its early stages, but Gluckman believes they can develop a reliable electrode that lasts for years and produces stronger, clearer signals.

Researchers have already demonstrated that humans can control computer cursors, robotic arms and even artificial voice boxes with today’s problematic electrodes. Yet the results are often short-lived.

“No one is going to let you operate on their brain twice,” Gluckman says. “If you want to directly animate limbs with an implant, the implant has to last the life of the patient. If we can do that, we can enable paraplegics to get around on their own.”

As Jackson notes, computers and smartphones may have powered silicon’s development, but the results are visible in everything from cars and digital thermometers to toys and even greeting cards.

Displays and solar cells are likely to power the new generation of flexible electronics, but brain implants are just one of the many unexpected directions they may take.

Enrique Gomez is assistant professor of chemical engineering, edg12@psu.edu. Thomas N. Jackson is Kirby Chair Professor of Electrical Engineering, tnj1@psu.edu. Susan Trolier-McKinstry is professor of ceramic science and engineering and director of the W.M. Keck Smart Materials Integration Laboratory, STMcKinstry@psu.edu. Bruce Gluckman is associate director of Penn State’s Center for Neural Engineering, bjg18@psu.edu.