MIT: Carbon nanotube transistors make the leap from lab to factory floor

The next major revolution in computer chip technology is now a step closer to reality. Researchers have shown that carbon nanotube transistors can be made rapidly in commercial facilities, with the same equipment used to manufacture traditional silicon-based transistors – the backbone of today’s computing industry. 

Carbon nanotube field-effect transistors (CNFETs) are more energy-efficient than silicon field-effect transistors and could be used to build a new generation of three-dimensional microprocessors. But until now, these devices have been mostly restricted to academic laboratories with only small numbers produced.

However, in a new study this month – published in the journal Nature Electronics – scientists have demonstrated how CNFETs can be fabricated in large quantities on 200-millimetre wafers: the industry standard for computer chip design. The CNFETs were created in a commercial silicon manufacturing facility and a semiconductor foundry in the United States.

Having analysed the deposition technique used to make the CNFETs, a team at the Massachusetts Institute of Technology (MIT) developed a way of speeding up the fabrication process by more than 1,100 times compared to previous methods, while also reducing the cost.

Their technique deposited the carbon nanotubes edge to edge on wafers, with CFNET arrays of 14,400 by 14,400 distributed across multiple wafers.

Max Shulaker, an MIT assistant professor of electrical engineering and computer science, who has been designing CNFETs since his PhD days, says the new study represents “a giant step forward, to make that leap into production-level facilities.”

Bridging the gap between lab and industry is something that researchers “don’t often get a chance to do,” he added. “But it’s an important litmus test for emerging technologies.”



For decades, improvements in silicon-based transistor manufacturing have brought down prices and increased energy efficiency in computing. Concerns are mounting that this trend may be nearing its end, however, as increasing numbers of transistors packed into integrated circuits do not appear to be increasing energy efficiency at historic rates. CNFETs are an attractive alternative technology because they are “around an order of magnitude more energy efficient” than silicon-based transistors, says Shulaker.

While silicon-based transistors are typically made at temperatures of 450 to 500 degrees Celsius, CNFETs can be manufactured at near-room temperatures.

“This means that you can actually build layers of circuits right on top of previously fabricated layers of circuits, to create a 3D chip,” Shulaker explains. “You can’t do this with silicon-based technology, because it would melt the layers underneath.” 

A 3D computer chip, which might combine logic and memory functions, is projected to “beat the performance of a state-of-the-art 2D chip made from silicon by orders of magnitude,” he says.

One of the most effective ways to build CFNETs in the lab is a method for depositing nanotubes called incubation – illustrated below – where a wafer is submerged in a bath of nanotubes until the nanotubes stick to the wafer’s surface.

The performance of the CNFET depends in large part on the deposition process, explains co-author Mindy Bishop, a PhD student in the Harvard-MIT Health Sciences and Technology program. This affects both the number of carbon nanotubes on the surface of the wafer and their orientation. They are “either stuck onto the wafer in random orientations like cooked spaghetti, or all aligned in the same direction like uncooked spaghetti still in the package.”

Aligning the nanotubes perfectly in a CNFET leads to ideal performance, but alignment is difficult to obtain, says Bishop: “It’s really hard to lay down billions of tiny 1-nanometre diameter nanotubes in a perfect orientation across a large 200-millimetre wafer. To put these length scales into context, it’s like trying to cover the entire state of New Hampshire in perfectly oriented, dry spaghetti.” 

While the incubation method employed by the MIT team is unable to perfectly align every nanotube (perhaps a breakthrough in future years may achieve this?), their experiments showed that it delivers sufficiently high performance for a CNFET to outperform a traditional silicon-based transistor. 

Furthermore, careful observations revealed how to alter the process to make it more viable for large-scale commercial production. For instance, Bishop’s team found that “dry cycling”, a method of intermittently drying out the submerged wafer, could drastically reduce the incubation time – from 48 hours to 150 seconds. Another new method called artificial concentration through evaporation (ACE) deposited small amounts of nanotube solution on a wafer, instead of submerging the wafer in a tank. The slow evaporation of the solution increased the overall density of nanotubes on the wafer. 

The researchers worked with Analog Devices, a commercial silicon manufacturing facility, and SkyWater Technology, a semiconductor foundry, to fabricate CNFETs using the improved methods. They were able to use the same equipment that the two facilities use to make silicon-based wafers, while also ensuring that the nanotube solutions met strict chemical and contaminant requirements of the facilities. 

The next steps, already underway, will be to build different types of integrated circuits out of CNFETs in an industrial setting and explore some of the new functions that a 3D chip could offer, adds Shulaker. 

“The next goal is for this to transition from being academically interesting to something that will be used by folks, and I think this is a very important step in this direction,” he concludes.

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